1. Field of the Invention
The present invention relates to an optical transceiver implemented with a micro-processor.
2. Related Prior Art
One type of an optical transceiver implements a controller that provides an electrically erasable and programmable read only memory (hereafter denoted as EEPROM) for users to write field data therein. A multi-source agreement regarding the SFP+ type optical transceiver has rules that the EEPROM with user rewritable area of 120 bytes is implemented. A Japanese Patent Application published as JP-H08-171545A has disclosed that the user rewritable EEPROM memory is realized by a flash memory integrated within a micro-controller unit (hereafter denoted as MCU) to reduce the number of components installed within the system.
The rewriting of such a flash memory is generally carried out by a block as one unit, while, the number of rewriting of the flash memory is often restricted by an inherent characteristic of the flash memory or by the specification of the system such as the SFP+ transceiver that installs a flash memory. Another Japanese Patent Application has disclosed to reduce the number of the writing or the erasing of the block in the flash memory by writing difference data in different blocks.
In the procedure that the difference data is written in the flash memory, a series of procedures to rearrange the rewritable area, to erase the flash memory and to write the rearranged data is necessary. Occasionally, it takes much time to complete these procedures and exceeds the standard time defined in the specification of the system such as the SFP+ optical transceiver. The SFP+ standard sets the execution time to rearrange the flash memory to be 40 mS, while, some microprocessors require a time to erase the flash memory implemented therein to be 36 mS and another time to write 120 bytes data to be 71 μs×120=8.52 mS, a total of 44.52 mS, which exceeds the time assigned to rearrange the flash memory in the SFP+ standard.
The preset application provides, in a system with a micro-controller implemented with a flash memory, a new algorithm to rearrange the data stored in the flash memory to shorten the process time thereof.